In a display apparatus that is connected to a computer, display is performed in synchronization with external vertical and horizontal synchronization signals. In particular, a clock of high accuracy is required to control the horizontal scanning lines based on the horizontal synchronization signal, and unless a jitter-free clock is provided, the display will be distorted or will undulate.
A circuit of the past is shown in FIG. 9, this circuit being formed by a crystal oscillator circuit 61, a frequency detection circuit 60, a phase comparator circuit 62, a filter 63, a VCO (voltage controlled oscillator) 64, and a 1/M frequency divider circuit 69.
The frequency detection circuit 60 counts the period of the horizontal synchronization signal 102 with the clock of the crystal oscillator circuit 61 that oscillates at a known frequency, and sets the divisor of the 1/M frequency divider circuit 69.
The phase of the output 205 of the 1/M frequency divider circuit 69 is compared to the phase of the horizontal synchronization signal 102 by the phase comparator circuit 62, the results thereof being smoothed by the filter 63, and used to control the VCO 64.
In this circuit, which is known as a phase-locked loop circuit, because a voltage that is smoothed by the filter 63 establishes the oscillation frequency of the VCO 64, if external noise or power supply noise is allowed to be superimposed, a variation will occur in the oscillation frequency of the VCO 64, thereby causing jitter in the system clock 204.
Additionally, regarding the frequency of the system clock 204 that is required with respect to the frequency of the horizontal synchronization signal 102 that is input, the divisor M of 1/M frequency divider circuit 69 is several thousand, so that the phase comparison is only performed for one clock out of several thousand clocks, the result being that it is difficult to apply feedback of the phase comparison results, thereby requiring time for the frequency to settle back to the original frequency when it is caused by change by external noise, this manifesting itself as noise-caused jitter.
A known technology for lessening the above-noted jitter is disclosed in the Japanese Unexamined Patent Publication (KOKAI) H2-14618.
Accordingly, it is an object of the present invention to provide a novel PLL circuit and clock generation method that improves on the above-noted problems, which particularly provides immunity with respect to external noise and power supply noise, and also enables the output of a stable clock with a constant phase.